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Integrated Circuit Systems, Inc.
ICS9250-26
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E type chipset. Provides three CPU speeds (66.6, 100, 133MHz) with SDRAM = 133.3MHz. Output Features: * 3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz achievable through I2C) * 9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz achievable through I2C) * 8 PCI (3.3 V) @33.3MHz * 2 IOAPIC (2.5V) @ 33.3 MHz * 2 Hublink clocks (3.3 V) @ 66.6 MHz * 2 USB (3.3V) @ 48 MHz ( Non spread spectrum) * 1 REF (3.3V) @ 14.318 MHz Features: * Supports spread spectrum modulation , down spread 0 to -0.5% and 0.25% center spread. * I2C support for power management * Efficient power management scheme through PD# * Uses external 14.138 MHz crystal * Alternate frequency selections available through I2C control.
Pin Configuration
*FS2//REF0 VDD0 X1 X2 GND0 GND1 3V66-0 3V66-1 VDD1 VDD2 PCICLK0 PCICLK1 PCICLK2 GND2 PCICLK3 PCICLK4 GND2 PCICLK5 PCICLK6 PCICLK7 VDD2 VDD3 GND3 GND4 48MHz_0 48MHz_1 VDD4 FS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GNDL1 IOAPIC0 IOAPIC1 VDDL1 CPUCLK0 VDDL0 CPUCLK1 CPUCLK2 GNDL0 GND5 SDRAM0 SDRAM1 VDD5 SDRAM2 SDRAM3 GND5 SDRAM4 SDRAM5 VDD5 SDRAM6 SDRAM7 GND5 SDRAM_F VDD5 PD# SCLK SDATA FS1
56-Pin 300mil SSOP
* This input has a 120K pull-down to GND.
Block Diagram
Functionality
FS2 X X 0 0 1 1 FS1 0 0 1 1 1 1 FS0 0 1 0 1 1 0 Function Tristate Test Active CPU = 66MHz SDRAM = 100MHz Active CPU = 100MHz SDRAM = 100MHz Active CPU = 133MHz SDRAM = 100MHz (Special Condition) Active CPU = 133MHz SDRAM = 133MHz
9250-26 Rev B 01/19/01 Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9250-26
ICS9250-26
General Description
The ICS9250-26 is a single chip clock solution for 810/810E type chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-26 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER 1 3 4 P I N NA M E FS2 REF0 X1 X2 TYPE OUT OUT OUT OUT PWR OUT PWR OUT OUT OUT IN IN IN OUT OUT PWR OUT PWR OUT DESCRIPTION Function Select pin. Determines CPU frequency, all output functionality (with 50) 3.3V, 14.318MHz reference clock output. Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3.3V power supply 3.3V PCI clock outputs, with Synchronous CPUCLKS 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 3. Data input for I2C serial input. Clock input of I2C input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V output running 100MHz. All SDRAM outputs can be turned off through I2C 3.3V free running 100MHz SDRAM not affected by I2C Ground for 2.5V power supply for CPU & APIC 2.5V Host bus clock output. 66MHz or 100MHz 133MHz depending on FS pins 2.5V power suypply for CPU & IOAPIC 2.5V clock outputs running at 33.3MHz.
47, 41, 35, 24, 23, GND (5:0) 17, 14, 6, 5 8, 7 3V66 [1:0]
44, 38, 33, 27, 22, VDD (5:0) 21, 10, 10, 9, 2 20,19,18,16, PCICLK (7:0) 15,13,12,11 26, 25 29, 28 30 31 32 48MHz (1:0) FS (1:0) SDATA SCLK PD#
36, 37, 39, 40, 42, SDRAM (7:0) 43, 45, 46 34 56,48 52, 50, 49 51, 53 54, 55 SDRAM_F GNDL (1:0) CPUCLK (2:0) VDDL (1:0) IOAPIC (1:0)
2
ICS9250-26
Maximum Allowed Current
810E Condition Powerdown Mode (PWRDWN# = 0 Full Active 66MHz SEL1, 0 = 10 Full Active 100MHz SEL1, 0 = 11 Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND 10mA 70mA 100mA Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 3.465V All static inputs = Vddq3 or GND 10mA 280mA 280mA
Clock Enable Configuration
PD# 0 1 CPUCLK LOW ON SDRAM LOW ON IOAPIC LOW ON 66MHz LOW ON PCICLK LOW ON REF, 48MHz LOW ON Osc OF F ON VCOs OFF ON
Power Groups*
VDD0, GND0 = REF & Crystal VDD1, GND1 = 3V66 VDD2, GND2 = PCICLK VDD3, GND3 = PLL core VDD4, GND4 = 48MHz VDD5, GND5 = SDRAM_F, SDRAM VDDL0, GNDL0 = CPUCLK VDDL1, GNDL1 = IOAPIC * To ensure the processor will power up to the desired frequency, the 3.3V supply to the ICS9250-26 needs to reach a stable condition before the 2.5V supply does. In most systems, the power up ramp of the 2.5V is slower than the 3.3V ramp. For those instances, no special requirements are necessary.
3
ICS9250-26
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
4
ICS9250-26
Byte 5: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit Bit7 Bit6 Bit5 FS2 (HW) 0 0 0 0 0 0 Bit (3,0) 0 0 1 1 1 1 1 1 1 1 Bit4 Bit2 Bit1 Desctiption ICS RESERVED BIT (Needs to be 0 clock to operate normal) ICS RESERVED BIT (Needs to be 0 clock to operate normal) ICS RESERVED BIT (Needs to be 0 clock to operate normal) Bit (3,0) FS0 (HW) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL1 (Bit3) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL0 (Bit0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK SDRAM MHz MHz 66.67 70.00 72.67 74.67 100.00 105.00 109.00 112.01 133.34 140.00 120.00 124.00 133.34 150.00 140.00 132.99 100.00 105.00 109.00 112.00 100.00 105.00 109.00 112.00 133.34 105.00 90.00 124.00 100.00 150.00 140.00 132.99 3V66 MHz 66.60 70.00 72.67 74.66 66.60 70.00 72.67 74.66 88.66 70.00 60.00 82.66 66.60 75.00 70.00 66.60 PCICLK MHz 33.30 35.00 36.33 37.33 33.30 35.00 36.33 37.33 44.33 35.00 30.00 41.33 33.30 37.50 35.00 33.30 0 1 1 XXXX Note 1 PWD 0 0 0
0 = Down Spread Spread Spectrum 0 to -.5% 1 = Center Spread Spread Spectrum .25% Not used (Needs to be 1 for normal clock operation) Not used (Needs to be 1 for normal clock operation)
Note1: Default at power-up will be for Bit 3 and Bit 0 to be 00, with external hardware selection of FS0, FS2 defining specific frequency.
5
ICS9250-26
Byte 0: Control Register (1 = enable, 0 = disable)
Name PWD Description Reserved ID 0 (Active/Inactive) Reserved ID 0 (Active/Inactive) Reserved ID 0 (Active/Inactive) Reserved ID 1 (Active/Inactive) SpreadSpectrum Bit 3 1 (Active/Inactive) (1=On/0=Off) Bit 2 26 48MHz 1 1 (Active/Inactive) Bit 1 25 48MHz 0 1 (Active/Inactive) Bit 0 49 CPUCLK2 0 (Active/Inactive) Note: Do not write in ID bits, these bits are for ICS internal use only. Must write a '1' in bit 0 after read back.
Byte 1: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4
Pin#
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 36 37 39 40 42 43 45 46
Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
PWD 1 1 1 1 1 1 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 20 19 18 16 15 13 12 -
Name PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 Reserved
PWD 1 1 1 1 1 1 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
6
ICS9250-26
Byte 3: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 4: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
7
ICS9250-26
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Paramete
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unles s otherwis e s tated) PA RA M ETER Input High Voltage Input Low Voltage Input High Current Input Low Current SYM BOL VIH VIL IIH IIL1 IIL2 M IN 2 VSS-0.3 VIN = VDD -5 VIN = 0 V; Inputs with no pull-up res is tors -5 VIN = 0 V; Inputs with pull-up res is tors -200 C L = 0 pF; Select @ 66 M Hz C L = 0 pF; Select @ 100 M Hz C L = 0 pF; Select @ 133 M Hz C L = M ax loads; Select @ 66 M Hz C L = M ax loads; Select @ 100 M Hz C L = M ax loads; Select @ 133 M Hz C L = 0 pF; Select @ 66 M Hz C L = 0 pF; Select @ 100 M Hz C L = 0 pF; Select @ 133 M Hz C L = M ax loads; Select @ 66 M Hz C L = M ax loads; Select @ 100 M Hz C L = M ax loads; Select @ 133 M Hz C L = M ax loads Input address VDD or GND VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1s t cros s ing of target frequency From 1s t cros s ing to 1% target frequency From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs ) Output dis able delay (all outputs ) 1 1 CONDITIONS TYP MAX VDD+0.3 0.8 5 UNITS V V A A 110 105 130 310 300 350 10 15 20 70 100 130 400 10 16 5 6 27 45 5 5 5 10 10 A M Hz nH pF pF pF ms ms ms ns ns mA
IDD3 .3 OP
2 -100 97 91 100 275 267 278 8 11 13 22 31 37 220 <1 14.318 7
mA
mA
Operating Supply Current
IDD2 .5 OP
mA
Powerdown Current Input Frequency Pin Inductance Input Capacitance Trans ition time Settling time
1 1 1 1
IDD3.3P D IDD.25P D Fi Lpin CIN COUT CINX Ttrans Ts TSTAB tP ZH ,tP ZL tP H Z,tP L Z
12
Clk Stabilization Delay
1 1
Guaranteed by des ign, not 100% tes ted in production.
8
ICS9250-26
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1
MIN 13.5 13.5 2 -27 27 0.4 0.4 45 40
TYP 16 21
RDSP2B 1 RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B
1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, 66, 100 MHz VT = 1.25 V, 133 MHz VT = 1.25 V VT = 1.25 V
MAX UNITS 45 45 V 0.4 V -27 30 1.6 1.6 55 55 175 250 mA mA ns ns % ps ps
-68 -9 54 11 1.1 1.1 49 48 65 90
Duty Cycle1 Skew window Jitter, Cycle-to-cycle1
1 1
tsk2B tjcyc-cyc2B
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1B 1 Output Impedance RDSN1B VO = VDD*(0.5) Output High Voltage VOH1 IOH = -1 mA IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 12 12 2.4 -33 30 0.4 0.4 45
TYP 14 14.5
MAX UNITS 55 55 V 0.55 V -33 38 1.6 1.6 55 175 500 mA mA ns ns % ps ps
-108 -9 95 29 1.2 1.2 49 65 120
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
9
ICS9250-26
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time
1
SYM BOL R DSP4 B
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MA X = 2.375 V VOL @ MIN = 1.2 V VOL @ MA X = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
M IN 9 9 2 -27 27 0.4 0.4 45
TYP 16 20
M A X UNITS 30 30 0.4 V V mA mA ns ns % ps ps
R DSN4 B VOH4B VOL4B IOH4B IOL4B tr4B tf4B dt4B
-68 -9 54 11 1.1 1.1 49 25 150
-27 30 1.6 1.6 55 250 500
1 1 1 1
Duty Cycle
Skew window
1
tsk4B tjcyc-cyc4B
Jitter, Cycle-to-cycle
Guaranteed by des ign, not 100% tes ted in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP3B 1 Output Impedance RDSN3B VO = VDD*(0.5) VOH @ MIN = 2.0 V IOH3 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL3 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 10 10 -54 54 0.4 0.4 45
TYP 12 15 -92 -16 68 29 1 1.5 52 85 120 150
MAX UNITS 24 24 -46 53 1.6 1.6 55 250 250 300 mA mA ns ns % ps ps
tr3 tf3 dt3 tsk3 tjcyc-cyc3
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, 66, 100 MHz VT = 1.5 V, 133 MHz
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
10
ICS9250-26
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1B 1 Output Impedance RDSN1B VO = VDD*(0.5) Output High Voltage VOH1 IOH = -1 mA IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 12 12 2.4 -33 30 0.4 0.4 45
TYP 15 15
MAX UNITS 55 55 V 0.55 V -33 38 2 2 55 500 500 mA mA ns ns % ps ps
-106 -14 94 29 1.3 1.4 51 250 150
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48M Hz_0 (Pin 25)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unles s otherwis e s pecified) PA RA M ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Ris e Time Fall Time
1
SYM BOL R DSP5 B 1 R DSN5 B VOH15 VOL5 IOH5 IOL5 tr5 tf5 dt5
1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @ MIN = 1.0 V VOH @ MA X = 3.135 V VOL @ MIN = 1.95 V VOL @ MA X = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, Fixed clocks VT = 1.5 V, Ref clocks
M IN 20 20 2.4 -29 29 0.4 0.4 45
TYP 29 27
M A X UNITS 60 60 0.55 V V mA mA ns ns % ps ps
-54 -11 54 16 1.1 1.6 53 130 650
-23 27 4 4 55 500 1000
1 1
Duty Cycle
Jitter, Cycle-to-cycle Jitter, Cycle-to-cycle
1
tjcyc-cyc5 tjcyc-cyc5
Guaranteed by des ign, not 100% tes ted in production.
11
ICS9250-26
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP3B 1 VO = VDD*(0.5) Output Impedance RDSN3B IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 VOH @ MIN = 2.0 V IOH3 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL3 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP 15 15
MAX UNITS 24 24 V 0.55 V -46 53 1.6 1.6 55 250 mA mA ns ns % ps
-82 -20 95 28 1.1 1.3 53 130
tr3 tf3 dt3 tjcyc-cyc3B
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
Duty Cycle Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Group Skews (CPU = 66 MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveform diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 Tsk1 CPU-SDRAM -3 CPU to SDRAM Skew CPU @ 1.25 V, SDRAM @ 1.5 V 1 0 Skew Window Tw1 CPU-SDRAM 1 Tsk1 CPU-3V66 7 CPU to 3V66 Skew CPU @ 1.25 V, 3V66 @ 1.5 V 1 Tw1 CPU-3V66 0 Skew Window 1 -500 SDRAM to 3V66 Skew Tsk1 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 1 0 Skew Window Tw1 SDRAM-3V66 1 Tsk1 3V66-PCI 1.5 3V66 to PCI Skew 3V66, PCI @ 1.5 V 1 Tw1 3V66-PCI 0 Skew Window 1 Tsk1 IOAPIC-PCI -1 IOAPIC to PCI Skew IOAPIC @ 1.25 V, PCI @ 1.5 V 1 Tw1 IOAPIC-PCI 0 Skew Window 1 Guaranteed by design, not 100% tested in production.
TYP -2.6 150 7.2 130 100 155 2.4 275 -0.4 0.25
MAX UNITS -2 ns 500 ps 8 ns 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns
12
ICS9250-26
Group Skews (CPU = 100 MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveform diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 Tsk2 CPU-SDRAM 4.5 CPU to SDRAM Skew CPU @ 1.25 V, SDRAM @ 1.5 V 1 Tw2 CPU-SDRAM 0 Skew Window 1 Tsk2 CPU-3V66 4.5 CPU to 3V66 Skew CPU @ 1.25 V, 3V66 @ 1.5 V 1 Tw2 CPU-3V66 0 Skew Window 1 -500 SDRAM to 3V66 Skew Tsk2 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 1 0 Skew Window Tw2 SDRAM-3V66 1 Tsk2 3V66-PCI 1.5 3V66 to PCI Skew 3V66, PCI @ 1.5 V 1 Tw2 3V66-PCI 0 Skew Window 1 Tsk2 IOAPIC-PCI -1 IOAPIC to PCI Skew IOAPIC @ 1.25 V, PCI @ 1.5 V 1 Tw2 IOAPIC-PCI 0 Skew Window 1 Guaranteed by design, not 100% tested in production. 1 Guaranteed by design, not 100% tested in production.
TYP 4.9 140 4.8 150 100 155 2.4 275 -0.4 0.25
MAX UNITS 5.5 ns 500 ps 5.5 ns 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns
Group Skews (CPU = 133 MHz)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF Refer to Group Offset Waveform diagram for definition of transition edges. PARAMETER SYMBOL CONDITIONS MIN 1 Tsk3 CPU-SDRAM -500 CPU to SDRAM Skew CPU @ 1.25 V, SDRAM @ 1.5 V 1 0 Skew Window Tw3 CPU-SDRAM 1 Tsk3 CPU-3V66 -500 CPU to 3V66 Skew CPU @ 1.25 V, 3V66 @ 1.5 V 1 Tw3 CPU-3V66 0 Skew Window 1 -500 SDRAM to 3V66 Skew Tsk3 SDRAM-3V66 SDRAM, 3V66 @ 1.5 V 1 0 Skew Window Tw3 SDRAM-3V66 1 Tsk3 3V66-PCI 1.5 3V66 to PCI Skew 3V66, PCI @ 1.5 V 1 Tw3 3V66-PCI 0 Skew Window 1 Tsk3 IOAPIC-PCI -1 IOAPIC to PCI Skew IOAPIC @ 1.25 V, PCI @ 1.5 V 1 Tw3 IOAPIC-PCI 0 Skew Window 1 Guaranteed by design, not 100% tested in production.
TYP 70 125 -145 220 100 155 2.4 275 -0.4 0.25
MAX UNITS 500 ps 500 ps 500 ps 500 ps 500 ps 500 ps 3.5 ns 500 ps 1 ns 1 ns
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ICS9250-26
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
Group Offset Waveforms
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ICS9250-26
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 56
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 18.288 MAX 18.542 MIN .720
D (inch) MAX .730
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9250yF-26-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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